library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;



entity reg_auto_dec is
	generic (
		size : integer := 32;
		Tpd : Time := unit_delay
	);
	port (
		clear : in bit;
		load : in bit;
		dec : in bit;
		d : in bit_vector(size-1 downto 0);
		q : out bit_vector(size-1 downto 0)
	);
end reg_auto_dec;


architecture reg_auto_dec_arh of reg_auto_dec is
begin
	process(clear, load, dec, d)
	variable data: integer;
	begin
			if clear = '1' then data := 0;
			elsif load = '1' then data := to_integer(d);
			elsif dec = '1' then data := data - 1;
			end if;
		q<= to_bits(data,size) after Tpd;
	end process;
end reg_auto_dec_arh;